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LXT6155 155 mbps sdh/sonet/atm transceiver datasheet the LXT6155 is a high speed fully integrated transceiver designed for 155 mbps sdh/sonet/ atm transmission system applications. the LXT6155 provides a lvpecl interface for fiber optics modules, and a cmi interface for coax cable drive. these circuits are implemented using level one?s proven low power 3.3v cmos analog and digital circuits. the transmitter incorporates a parallel-to-serial converter, a frequency multiplier pll, cmi line encoders, and line interfaces for both coax cable and optical fiber. the receiver incorporates an adaptive equalizer, a clock recovery pll, loss of signal (los) detector, cmi and nrz decoders, a serial-to-parallel converter, and an sdh/sonet frame byte detector/aligner. at the system interface, the LXT6155 offers both parallel 8-bit and serial differential interfaces. the LXT6155 also operates in either hardware stand-alone mode or software mode. software mode is controlled by a serial microprocessor ( p) to program formats and operating/test modes. product features applications oc3/stm1 sdh/sonet cross connects oc3/stm1 sdh/sonet add/drop mux oc3/stm1 transmission systems oc3/stm1shorthaulseriallinks oc3/stm1 atm/wan transmission systems oc3/stm1 atm/wan access systems features complies with: ? bellcore sonet gr-253 ? itu-t g.703/813/958 stm1 two line interface formats: ?fiber lvpecl nrz ?coax cmi transmit synthesizer pll receive clock recovery pll adaptive cmi equalizer analog circuitry for transformer drive programmable los function cmi encoder and decoder serial/parallel and parallel/serial conversion byte alignment for sdh/sonet frames two modes of operation: ? microprocessor controlled; software mode ? stand-alone; hardware mode no external crystal required. a 19.44 mhz crystal is optional low power consumption (less than 760 mw typical) operates from a single 3.3 v supply 64 pin lqfp package order number: 249612-001 january 2001
datasheet information in this document is provided in connection with intel ? products. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties rel ating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products a re not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the name of product may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product order. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtained by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 2001 *third-party brands and names are the property of their respective owners.
datasheet 3 155 mbps sdh/sonet/atm transceiver ? LXT6155 contents 1.0 pin assignments and signal descriptions ......................................................8 2.0 functional description ...........................................................................................13 2.1 transmitter ..........................................................................................................13 2.1.1 transmitted signal .................................................................................13 2.1.1.1 fiber based g.957/gr-253 transmission systems ................. 13 2.1.2 coax based g.703/gr-253 transmission systems ..............................13 2.1.2.1 cmi encoding ............................................................................14 2.1.3 tx clock monitoring................................................................................14 2.2 receiver ..............................................................................................................14 2.2.1 analog front end and timing recovery ................................................14 2.2.1.1 cmi mode..................................................................................14 2.2.1.2 nrz mode .................................................................................15 2.2.2 receive frame detect and byte alignment ...........................................15 2.2.2.1 loss of signal (los) ................................................................. 16 2.2.2.2 coax interface ...........................................................................16 2.2.2.3 fiber interface ...........................................................................16 2.3 clocks..................................................................................................................18 2.3.1 parallel mode .........................................................................................18 2.3.1.1 transmit parallel input clock (tpiclk) ....................................18 2.3.1.2 receive parallel output clock (rpoclk) ................................18 2.3.2 serial mode ............................................................................................18 2.3.2.1 transmit serial input clock (tsiclkp/tsiclkn).....................18 2.3.2.2 receive serial output clock (rsoclkp/rsoclkn) ..............18 2.3.3 crystal reference clock (xtalin/xtalout) .......................................19 2.4 jitter.....................................................................................................................1 9 2.4.1 jitter tolerance.......................................................................................19 2.4.2 jitter generation (intrinsic jitter) ............................................................19 2.4.3 jitter transfer .........................................................................................19 2.5 operational modes .............................................................................................. 19 2.5.1 hardware mode......................................................................................20 2.5.1.1 pll clock reference (cis pin) .................................................20 2.5.1.2 loopback test (rlis and llis pins) ........................................21 2.5.1.3 line interface selection (mode pin) ........................................21 2.5.1.4 parallel/serial mode selection (sp pin) ....................................21 2.5.1.5 tx amplitude trim .....................................................................21 2.5.2 software mode .......................................................................................22 2.5.2.1 serial input clock (sclk) ......................................................... 22 2.5.2.2 chip select input (cs)...............................................................22 2.5.2.3 serial input word (sdi) ............................................................. 22 2.5.2.4 serial output word (sdo).........................................................22 2.6 serial system interface .......................................................................................23 2.7 parallel system interface ....................................................................................23 2.8 loopback modes .................................................................................................24 2.8.1 local loopback ...................................................................................... 24 2.8.2 remote loopback .................................................................................. 25
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 4 datasheet 3.0 register definitions ................................................................................................ 26 4.0 application information .........................................................................................33 4.1 fiber optic module interface............................................................................... 33 4.2 coax interface .....................................................................................................33 5.0 test specifications .................................................................................................. 37 6.0 mechanical specifications ................................................................................... 48 7.0 notes ............................................................................................................................. 49 figures 1 LXT6155 pin assignments ................................................................................. 8 2 LXT6155 system interface.................................................................................. 14 3 framing state...................................................................................................... 16 4 criteria for los output .......................................................................................16 5 receive frame synchronization and frame pulse position ............................... 17 6 example of cmi encoded binary signal ............................................................. 17 7 hardware mode................................................................................................... 20 8 software mode .................................................................................................... 23 9 serial data output word structure (read cycle: r/w=high) ............................. 23 10 serial data input word structure (write cycle: r/w = low)............................... 23 11 serial interface .................................................................................................... 24 12 parallel interface ................................................................................................. 24 13 local loopback ................................................................................................... 25 14 remote loopback ............................................................................................... 25 15 rx digital 2, register #13 (address a<3:0>=11001) ..........................................31 16 3.3 v lvpecl to 3.3 v lvpecl interface.......................................................... 34 17 75 w coax cable interface ................................................................................. 35 18 transmit parallel input data timing (see table 28) ........................................... 38 19 transmit serial input data timing (see table 28) .............................................. 38 20 receive serial output data timing (see table 30) ............................................40 21 receive parallel output data timing (see table 30) ......................................... 40 22 microprocessor input timing diagram ................................................................ 42 23 microprocessor output timing diagram ............................................................. 42 24 cmi encoded zero per g.703 and sts-3 ........................................................... 43 25 cmi encoded one per g.703 and sts-3 ........................................................... 43 26 jitter tolerance ................................................................................................... 44 27 generation measurement filter characteristics................................................. 45 28 typical coax jitter transfer ................................................................................ 46 29 typical fiber jitter transfer ............................................................................... 47 30 LXT6155le package specification..................................................................... 48
datasheet 5 155 mbps sdh/sonet/atm transceiver ? LXT6155 revision history
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 6 datasheet
datasheet 7 155 mbps sdh/sonet/atm transceiver ? LXT6155 figure 1. LXT6155 block diagram data recovery clock recovery pll serial/ parallel divide 8 rtip rring frame detect & byte aligner adaptive equalizer ttip0 tring0 cmi encode ttip1 tring1 x 8 synthesizer pll parallel/ serial rsoclkp, rsoclkn rpoclk rpod<7:0> rpos, rneg los rofp/cmierr tpos, tneg tpid<7:0> tsiclkp, tsiclkn tpiclk local loopback 8 2 2 loss of signal (los) frequency doubler 2 2 8 remote loopback control logic control registers 4 hwsel rlis, llis 2 xtalin xtalout optional 19.4mhz crystal equalizer control cmi/nrz decode lock rxish txish m p control (cs, sclk, sdi, sdo), hardware (mode0, sp, cis, rife)
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 8 datasheet 1.0 pin assignments and signal descriptions figure 1. LXT6155 pin assignments vbias ravcc los lock rofp/cmierr rdgnd rdvcc atst rpos rneg pvcc rsoclkn rsoclkp gnd rpod0 rpod1 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LXT6155le tvcc tring1 ttip0 tring0 tgnd well sub ttip1 hwsel addr1/llis addr0/rlis ragnd rtip rring ragnd rxish 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 xtalin tagnd txish tavcc tdvcc tsiclkp tsiclkn xtalout tpos tneg tdgnd cs /mode sclk/sp sdi/cis sdo/rife tpid7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 rpod2 rpod4 rpod5 rpod6 rpod7 rpoclk vcc rpod3 tpiclk tpid0 tpid1 tpid2 tpid3 tpid4 tpid5 tpid6 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 (top view)
datasheet 9 155 mbps sdh/sonet/atm transceiver ? LXT6155 table 1. LXT6155 pin descriptions pin # symbol i/o 1 type 2 description 1 xtalin ai/o crystal input/output . these pins are connected to an external 19.44 mhz crystal. alternately, a stable external clock signal may be connected to xtalin with xtalout left open. xtalin should be connected to tagnd and xtalout should be left open if the transmit input clock is used as a clock reference 2xtalout 3tagnds transmit analog ground. 4 txish ai/o transmit pll loop filter pin. connecting a capacitor to tagnd from this pin controls the tx pll transfer function. this pin requires a 68nf captotagnd. 5tavccs transmit analog power supply. 6 tdvcc s transmit digital power supply. 7 tsiclkp di lvpecl transmit serial input clock, positive and negative . differential transmit clocks at 155.52 mhz. these pins are disabled when parallel mode is selected. 8 tsiclkn 9 tpos di lvpecl transmit serial input data, positive and negative. differential input data from an overhead terminator at 155.52 mbps, clocked in by tsiclk. these pins are disabled when parallel mode is selected. 10 tneg 11 tdgnd s transmit digital ground. 12 cs/mode di ttl chip select input, software mode (hwsel = high). register transactions through the p interface are initiated by the falling edge of this signal. line interface mode, hardware mode (hwsel =low).setsline interfacemodetolvpecl(mode=low)orcmi(mode=high). 13 sclk/sp di ttl serial clock input, software mode (hwsel = high). serial microprocessor uses this pin to clock in/out data. sclk can be from 0 to 4.096 mhz. serial/parallel select, hardware mode (hwsel =low).when sp = low, serial systems interface is used. when sp = high, 8 bit parallel system interface is used. 14 sdi/cis di ttl serial input data, software mode (hwsel = high). the serial data is applied to this pin when the LXT6155 operates in software mode. sdi is sampled on the rising edge of sclk. clock input select, hardware mode (hwsel = low). cis sets the reference clock for centering the rx pll. if cis = low, then the LXT6155 uses the transmit input clock as the reference. if cis = high, then the LXT6155 uses the crystal clock input (xtalin) as the reference. 15 sdo/rife di/o ttl serial output data, software mode (hwsel = high). the serial data from the on-chip register is output on this pin in software mode. data output is valid on the rising edge of sclk. this pin goes to a high impedance state when the serial port is being written to or when cs is high. receive input frame enabler, hardware mode (hwsel = low). the frame detection option is available only in parallel mode. if rife = low, then the LXT6155 disables the frame detection, and byte alignment. if rife = high, then the LXT6155 enables the frame detection, and outputs rpod bytes aligned to the sonet/sdh framer. this feature, if used, must be enabled prior to applying data to rtip/rring. 1. di = digital input; do = digital output; di/o = digital input/output; ai = analog input; ao = analog output; ai/o = analog input/output; s=supply. 2. ttl = transistor-to-transistor logic (5v tolerant); lvpecl = low-voltage positive ecl.
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 10 datasheet 16 17 18 19 tpid7/txtrim3 tpid6/txtrim2 tpid5/txtrim1 tpid4/txtrim0 di ttl transmit parallel input data . transmit data from an overhead terminator at parallel speed 19.44 mhz, clocked in by tpiclk. tpid7 is the most significant bit, and is the first bit to be sent. these pins should be grounded or not connected when the LXT6155 is used in serial mode. transmit trim controls , in serial, hardware, coax mode only. these pins trim the amplitude of the line driver output from (nom -21%) to (nom +24%) in 3% steps. this feature is only enabled when pin #20 (txtrimena) is high. 20 tpid3/txtrimena di ttl transmit parallel input data . transmit data from an overhead terminator at parallel speed 19.44 mhz, clocked in by tpiclk. tpid7 is the most significant bit, and is the first bit to be sent. these pins should be grounded or not connected when the LXT6155 is used in serial mode. transmit trim enable , in serial, hardware, coax mode only. this pin enables the trimming of the line driver output by pins 16-19 when high. 21 22 23 tpid2 tpid1 tpid0 di ttl transmit parallel input data . transmit data from an overhead terminator at parallel speed 19.44 mhz, clocked in by tpiclk. tpid7 is the most significant bit, and is the first bit to be sent. these pins should be grounded or not connected when the LXT6155 is used in serial mode. 24 tpiclk di ttl transmit parallel input clock . parallel transmit clock at 19.44 mhz. this pin is disabled when serial mode is selected and should be grounded or not connected. 25 vcc s power supply . 26 rpoclk do ttl receive parallel output clock . parallel receive clock as recovered from received data. the clock is nominally 19.44 mhz, synchronized with rpod<7:0>. 27 28 29 30 31 32 33 34 rpod7 rpod6 rpod5 rpod4 rpod3 rpod2 rpod1 rpod0 do ttl receive parallel output data . rpod<7:0> output aligned 8-bit bytes at rpoclk clock rate. these pins are to be left open when serial mode is selected. rpod7 is the most significant bit, and is the first to arrive. 35 gnd s ground . 36 rsoclkp do lvpecl receive serial output clock . serial receive clock as recovered from received data. the clock is nominally 155.52 mhz, synchronized with output serial data rpos and rneg. 37 rsoclkn 38 pvcc s pecl buffers power supply . 39 rneg do lvpecl receive serial output data, positive and negative .thesetwopins provide recovered data synchronized to receive serial output clocks rsoclkp and rsoclkn. these pins are tristated and should be left open when parallel mode is selected. 40 rpos 41 rdvcc s receive digital power supply . 42 rdgnd s receive digital ground . table 1. LXT6155 pin descriptions (continued) pin # symbol i/o 1 ty pe 2 description 1. di = digital input; do = digital output; di/o = digital input/output; ai = analog input; ao = analog output; ai/o = analog input/output; s=supply. 2. ttl = transistor-to-transistor logic (5v tolerant); lvpecl = low-voltage positive ecl.
datasheet 11 155 mbps sdh/sonet/atm transceiver ? LXT6155 43 rofp/ cmierr do ttl receive output frame pulse . in hardware mode (hwsel =low),this pin is asserted (high) on the last a2 byte in the (a1.....a1, a2.....a2) sequence in the rpod<7:0> traffic. a1=1111,0110 and a2=0010,1000 in binary. in software mode (hwsel = high), this position is programmable. during coax operation, when frame detection is disabled (rife = 0 in hw/reg #12, bit3 = 0), or in serial mode, this pin indicates cmi line code errors. these pulses are 50 ns wide (active high). one or more errors in 16 consecutive bits will causes a single pulse. 44 lock do ttl receive output pll lock . a high indicates receive pll has locked to incoming data. a low indicates receive pll is not locked. 45 los do ttl loss of signal . an alarm output signal (high) indicating incoming signal voltage is weak or incoming data does not contain enough transitions. in software mode (hwsel = 1) this pin can be configured to combine los and lock alarms. 46 ravcc s receive analog power supply . 47 atst - analog test . for factory test purposes only; do not connect. 48 vbias ai analog bias input voltage. this pin requires a 15k (1%) pull-down resistor to ragnd. 49 rxish a0 analog rx pll external cap. connecting a capacitor to ragnd from this pin controls the rx pll transfer function. this pin requires a 330nf cap to ragnd. 50 ragnd s receive analog ground . 51 rring ai analog receive input data, positive (rtip) and negative (rring) .accepts incoming signals (lvpecl or cmi) from the line interface. 52 rtip 53 ragnd s receive analog ground . 54 addr0/rlis di ttl address 0, software mode (hwsel = high). this pin together with addr1 sets the chip select address. up to 4 LXT6155 chips can be addressed by the p interface. remote loopback input select, hardware mode (hwsel =low). together with llis sets LXT6155 in a loopback test mode. see table 4 55 addr1/llis di ttl address 1, software mode (hwsel = high). this pin together with addr0 sets the chip select address. up to 4 LXT6155 chips can be addressed by the p interface. local loopback input select, hardware mode (hwsel =low). together with rlis sets the LXT6155 in remote loopback mode. see ta ble 4 56 hwsel di ttl hardware/software mode select .whenhwsel = high, LXT6155 enters software (host) mode, and is ready to communicate with a serial microprocessor. when hwsel = low, LXT6155 operates in hardware standalone mode (without a serial p). 57 sub s reserved . must be connected to gnd. 58 well s reserved . must be connected to vcc. 59 tgnd s transmit analog ground . 60 tring0 ao transmit output data, positive (ttip0) and negative (tring0) . differential cmi driver outputs for coax interface. 61 ttip0 table 1. LXT6155 pin descriptions (continued) pin # symbol i/o 1 type 2 description 1. di = digital input; do = digital output; di/o = digital input/output; ai = analog input; ao = analog output; ai/o = analog input/output; s=supply. 2. ttl = transistor-to-transistor logic (5v tolerant); lvpecl = low-voltage positive ecl.
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 12 datasheet 62 tring1 do transmit output data, positive (ttip1) and negative (tring1) . differential lvpecl nrz driver outputs for a fiber optic transceiver. 63 ttip1 64 tvcc s transmit analog power supply . table 1. LXT6155 pin descriptions (continued) pin # symbol i/o 1 ty pe 2 description 1. di = digital input; do = digital output; di/o = digital input/output; ai = analog input; ao = analog output; ai/o = analog input/output; s=supply. 2. ttl = transistor-to-transistor logic (5v tolerant); lvpecl = low-voltage positive ecl.
datasheet 13 155 mbps sdh/sonet/atm transceiver ? LXT6155 2.0 functional description the LXT6155 is a front-end transceiver designed for 155 mbps oc3/stm1/atm transmission applications. table 2 lists the standards with which the LXT6155 is compliant. the LXT6155 interfaces to either a fiber transceiver or a coax cable on the line side, and on the system side, to an sdh/sonet overhead terminator or an atm uni. the LXT6155 can function in hardware stand-alone mode, or in software mode controlled through an industry standard motorola compatible 4-wire serial microprocessor interface. the LXT6155 can be set to operate in either cmi mode for the 75 ? coax interface or nrz mode for the optical transceiver interface. the operating mode can be set in either hardware mode by using the mode pin, or software mode by using primary control register, bit 0. 2.1 transmitter in serial mode, the LXT6155 accepts both data (tpos, tneg) and clock signals (tsiclkp, tsiclkn). serial clock signals are required for the LXT6155 to run internal logic, reshape the line transmit pulses and generate the low-jitter clocks for tx data generation. in parallel mode, the LXT6155 accepts data tpid<7:0> and clock tpiclk. tpiclk is internally multiplied by 8 to yield the 155.52 mhz clock for tx data generation. both serial and parallel clocks (tsiclkp/tsiclkn and tpiclk) must conform to the sonet/ sdh standard frequency accuracy requirements. depending on whether the selected media interface is coax or fiber, the data is cmi or nrz encoded respectively, and passed to the appropriate line drivers. the LXT6155 line drivers are high-speed buffers that meet the cmi templates and industry standard lvpecl signal requirements. the cmi output pins are ttip0 and tring0, and the nrz lvpecl pins, ttip1 and tring1. 2.1.1 transmitted signal transmitted signals conform to the standard templates listed in table 2. 2.1.1.1 fiber based g.957/gr-253 transmission systems the LXT6155 provides 3.3v lvpecl compatible signals for interfacing to a fiber optic transceiver. please refer to application information for interface schematics. 2.1.2 coax based g.703/gr-253 transmission systems the LXT6155 encodes and decodes cmi signals that are transmitted onto a 75 ? coax cable compliant with stm1/sts-3 cmi templates. please refer to the cmi templates shown in figures 24 and 25.
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 14 datasheet figure 2. LXT6155 system interface 2.1.2.1 cmi encoding coded mark inversion (cmi) is an encoding scheme adopted by sonet sts-3 and sdh stm1 standards. cmi encoding guarantees at least one transition per bit, thereby enhancing the clock recovery process. cmi encodes a ?0? with a midpoint positive transition, and a ?1? as low or high, in opposite polarity to the previous encoded ?1?. refer to figures 6, 24 and 25 for encoding and pulse template information. 2.1.3 tx clock monitoring the LXT6155 provides transmit clock monitoring for both serial and parallel operating modes. when using the crystal clock as a reference, the LXT6155 monitors the tsiclkp/tsiclkn or the tpiclk input(s) for transitions. if no transition is seen within 200ns, the tx_clk_alarm flag will be set (reg #15) and the transmitter outputs ttip1/tring1 or ttip0/tring0 will stop sending data to the line. this condition will remain until the LXT6155 detects clock transitions at the transmitter input(s) tsiclkp/tsiclknortpiclk.transmitclockmonitoringcanbedisabledinsoftwaremode only. in remote loopback, transmit clock monitoring is disabled in sw and hw mode. in sw mode, when using transmit clocks as the receive pll reference, the user must disable transmit clock monitoring bysettingreg#1bit<0>low. 2.2 receiver 2.2.1 analog front end and timing recovery 2.2.1.1 cmi mode received data on rtip/rring goes through an adaptive equalizer. an adaptive equalizer and adaptive automatic gain control (agc) compensate the frequency-and-cable length dependent loss in data signal, and reshapes the signal to the optimal waveform. a phase locked loop (pll) tx rx processor (optional) LXT6155 4 fiber optic modules or coax transformers 2 2 sonet/sdh overhead terminator atm uni 1 2 1 2 data/clock (8-bit parallel or serial mode) data/clock (8-bit parallel or serial mode) receive output frame pulse (rofp) receive ouput pll lock (lock) loss of signal (los) system interface line interface f
datasheet 15 155 mbps sdh/sonet/atm transceiver ? LXT6155 then performs clock recovery operation, comparing the reshaped data phase against the receive output clock phase. the receive pll requires an external reference (e.g. transmit input clock or xtal clock) to start up the clock recovery process. this clock can be derived from xtalin, tpiclk or tsiclk ( 8). the recovered clock is used to retime the cmi signals, and to decode cmi to nrz. coding errors are detected and flagged via the cmierr pin in hw mode with the frame detect disabled or in serial mode. in software mode (hwsel = high) cmi coding errors are indicated via the p interface interrupt register: reg #15, mode 05. 2.2.1.2 nrz mode the on chip adaptive equalizer is bypassed. data goes straight to the clock recovery phase locked loop. the pll then performs clock recovery operation, comparing the data phase against the clock phase. this clock can be derived from xtalin, tpiclk or tsiclk ( 8). the receive pll requires an external reference (e.g. transmit input clock or xtal clock) to start up the clock recovery process. the recovered clock is used to retime the data signals. when the recovered clock is within 488 ppm of the reference clock, the lock signal asserts. this alarm is also accessible on the p interface as a status bit (reg #15, mode 0) and as an interrupt (reg #15, mode 05). once the recovered clock has been obtained and the nrz data has been recovered, the LXT6155 performs frame-detect-and- byte-alignment, and serial-to-parallel conversion. the LXT6155 optionally provides output data rpod<7:0> aligned to the sdh/sonet byte boundary. the user has the option to enable/disable the frame-alignment function in both hardware and software mode. the frame detect/byte alignment function generates the receive output frame pulse (rofp). in hw mode (hwsel = low) rofp asserts (high) on the third a2 byte. in sw mode (hwsel = high) this position is programmable via register #13, bits <6:3>. when byte alignment is disabled and the LXT6155 is in cmi mode, the rofp pin indicates cmi coding errors including polarity errors for ones and inversion errors for zeroes. the clock recovery pll?s center frequency comes from either the local crystal or a stable transmit input clock (tsiclkp/tsiclkn or tpiclk). if operated in loop-timed mode or remote loopback mode, an external reference clock must be used to center the internal pll clock. in remote loopback, the receive reference remains either xtalin or tsiclk or tpiclk, depending on the control selection. if an independent and stable transmit clock is available, the designer has the option of applying this clock to pin xtalin to center the pll, without the external crystal. the user can also replace the crystal by connecting the tpiclk (19.44mhz) signal to the xtalin pin. however, a local crystal is recommended for ?keep alive? purposes in case the clock becomes unavailable. 2.2.2 receive frame detect and byte alignment receive frame detection only operates in parallel mode, if frame detection is enabled. the LXT6155 provides aligned bytes rpod<7:0> following the distinct sonet oc3/stm1 frame marker word, 3 x a1, followed by 3 x a2, where a1=f6h and a2=28h. the receive output frame pulse (rofp) asserts during the third a2 byte, and de-asserts after one complete rpoclk clock period. if this feature is used, it can be enabled in register #12 bit <3> in software mode 1 ,orby setting the rife (pin 15) high in hardware mode prior to applying data to rtip/rring. two consecutive frames with correct frame words (a 1 ...a 1 a 2 ...a 2 ) are required to change from an out- of-frame state (oof) to an in-frame state. the oof alarm is accessible in sw mode (hwsel = high) as a status or interrupt signal (reg #15). to declare an oof condition, four consecutive 1. for further details see register #12 description for usage.
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 16 datasheet frames with incorrect frame words are required. byte alignment occurs when entering the in-frame state. in case of an oof event, the byte alignment and frame pulse position are frozen. the rofp output continues unchanged until re-entering the in-frame state. figure 3. framing state 2.2.2.1 loss of signal (los) loss of signal provides an alarm signal indicating incoming signal voltage is weak or incoming data does not contain enough transitions. this signal is available in hw mode on pin #45 and in sw mode as status and interrupt (reg #15, modes 00 and 05). 2.2.2.2 coax interface loss of signal provides an alarm output that indicates weak line input signal. the los signal asserts when the incoming signals fall below a specified loss threshold, and de-asserts when the line signal rises nominally 2db above the assert threshold. the threshold is adjustable in sw mode (hwsel = high) via the processor interface. 2.2.2.3 fiber interface if no transition is detected during any 3112 bit times (20 sec), los asserts. los is cleared when two consecutive frame words with no los events between then are received. in sw mode (hwsel = high) the assertion window is programmable from 128 bits to 4096 bits in four steps. the deassertion criteria can also be configured to 12.5% transition density. the 12.5% density is determined by receipt of at least 4 transitions during a 32 bit sliding window. figure 4. criteria for los output in frame 4 consecutive frames with errored fas 2 consecutive frames with correct fas out of frame nominal value los de-assert los assert level below nominal hys = 3 db
datasheet 17 155 mbps sdh/sonet/atm transceiver ? LXT6155 figure 5. receive frame synchronization and frame pulse position figure 6. example of cmi encoded binary signa l a2 j0 z0 z0 a1 a2 a2 a1 a1 start of spe end of previous frame 1100 1101 1011 1110 0000 1000 1001 0001 1010 0100 0011 0101 0010 0111 0110 1111 -4 -5 -3 -6 0 -1 +1 -2 +4 +3 +5 +2 +7 +6 -7 ch dh bh eh 0h 8h 9h 1h ah 4h 3h 5h 2h 7h 6h fh rpoclk rpod <7:0> contents of reg 13h hex binary table 2. standards compliance item sdh/sonet (fiber) sdh/sonet (coax) stm1 oc3 stm1 sts-3 line rate (mbps) 155 155 155 155 line interface 50 ? lvpecl 50 ? lvpecl 75 ? coax 75 ? coax line code nrz nrz cmi cmi signal templates g. 9 5 7 stm1 eye oc3 oc3 eye g. 7 0 3 cmi template. cmi eye stsx-3 cmi template. cmi eye jitter g. 9 5 8 g. 8 2 5 gr-253 g.813 g. 8 2 5 gr-253 00 0 1 111 binary cmi t/2 t/2 t
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 18 datasheet 2.3 clocks 2.3.1 parallel mode the LXT6155 accepts tpiclk synchronized with transmit input parallel data tpid<7:0>. the data is serialized and transmitted at ttip0/tring0 or ttip1/tring1 depending on which line encoding mode is selected. the LXT6155 in turn produces the receive output parallel clock rpoclk, that is recovered from incoming line data rtip/rring, and is synchronized with receive output parallel data rpod<7:0>. 2.3.1.1 transmit parallel input clock (tpiclk) tpiclk is the transmit parallel input clock provided by the systems interface. this clock must be nominally 19.44 mhz, synchronized with parallel input data tpid<7:0>. this clock is then internally multiplied by 8 to produce a serial clock, used for parallel-to-serial conversion, line drivers, and pulse reshaping. in hw mode (hwsel = low), tpid data is sampled on the falling edge of tpiclk. in sw mode (hwsel = high), the clock polarity can be inverted (reg #0, bit #3). 2.3.1.2 receive parallel output clock (rpoclk) rpoclk is the parallel output clock that is recovered from the line input data rtip/rring. this clock is at 19.44 mhz, synchronized with parallel output data rp0d<7:0>. in hw mode (hwsel = low), the rpoclk clock rising edge is at the center of eye opening of rpod<7:0> as shown in figure 21. in sw mode (hwsel = high), the clock polarity can be inverted (reg #0, bit #2). under los (los=high) or rx pll loss of lock (lock=low) conditions rpoclk is switched to the reference selected by the cis control in hw mode, or reg #0 bit #5 in sw mode. also, the parallel output is forced to all zeros. this feature can be disabled in sw mode (hwsel =high) via register #10, bit #7. 2.3.2 serial mode at the transmit systems interface, the LXT6155 accepts the transmit input clock tsiclkp/ tsiclkn that is synchronized to incoming serial differential data tpos/tneg. at the line interface, the LXT6155 accepts rtip/rring data and produces the clocks rsoclkp/ rsoclkn synchronized to receive output data rpos/rneg. rsoclkp/rsoclkn clock edges are at the center of rpos/rneg. 2.3.2.1 transmit serial input clock (tsiclkp/tsiclkn) tsiclkp/tsiclkn is the serial input clock from the overhead terminator. this 155.52 mhz clock is rising edge centered with input serial data on tpos and tneg. these clock pins should be left open when the LXT6155 operates in parallel mode. 2.3.2.2 receive serial output clock (rsoclkp/rsoclkn) rsoclkp/rsoclkn is the serial clock recovered from the line input data on rtip/rring. this 155.52 mhz clock is falling edge centered with receive serial output data on rpos/rneg. these clock pins should be left open when the LXT6155 operates in parallel mode. under los
datasheet 19 155 mbps sdh/sonet/atm transceiver ? LXT6155 (los=high) or rx pll loss of lock (lock=low) conditions rsoclk p/n is switched to the tx serial clock. also the serial output data is forced to all zeros. this feature can be disabled in sw mode (hwsel = high) via register #10, bit #7. 2.3.3 crystal reference clock (xtalin/xtalout) an optional 19.44 mhz crystal can be connected across the xtalin and xtalout pins. this crystal reference provides an onchip clock that is independent of the external system clock (tsiclkp/tsiclkn or tpiclk). the main functions of the crystal reference clock are threefold: (1) to center the receive pll at 155 mhz, (2) to keep the pll centered at 155 mhz when los asserts, and (3) in the event incoming data is lost, to provide a reference clock for other devices which require it. the designer has the option to use this crystal reference clock or the transmit input clock (tsiclkp/tsiclkn or tpiclk) to center the receive pll. 2.4 jitter the bellcore gr-253 standard defines jitter as the ?short-term variations of a digital signal?s significant instants from their ideal positions in time?. significant instants are the optimum data sampling instants. jitter parameters can be measured at the line interface, with system interface in loopback mode, yielding jitter accumulated in both transmitter and receiver. isolated jitter measurements for transmitter and receiver can also be performed. jitter specs are divided into three categories: jitter tolerance, jitter generation, and jitter transfer. jitter values, in effect, measure the performance of the receive pll and the transmit synthesizer pll. 2.4.1 jitter tolerance jitter tolerance is the peak-to-peak amplitude of sinusoidal jitter applied at the line interface input that causes an equivalent 1 db snr loss measured as ber = 10 -10 .refertofigure26onpage page 44 for the LXT6155 performance. 2.4.2 jitter generation (intrinsic jitter) jitter generation is the amount of transmit jitter at the output of the equipment with a jitter-free transmit input data and clock. for sonet/sdh, jitter generation is less than 0.01 ui rms, measured with a band-pass filter from 12 khz to 1.3 mhz. refer to 27 on page 45 for the LXT6155 performance. 2.4.3 jitter transfer jitter transfer is defined as the ratio of output jitter to input jitter amplitude versus jitter frequency for a given bit rate. input jitter amplitude is shown in the jitter tolerance curve. output jitter is under the jitter transfer template. refer to figures 27 and 28 on pages and for the LXT6155 performance. 2.5 operational modes the LXT6155 functions in both hardware standalone and software modes. the operating mode is set by the state of the hwsel pin.
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 20 datasheet 2.5.1 hardware mode by setting hwsel = low, the LXT6155 operates in standalone hardware mode, without a serial microprocessor interface. a subset of the functions available in the software mode can be set in hardware mode. LXT6155 provides a comprehensive flexibility in configuring system clock preference settings, as well as providing pins for activating loopback test modes. tables 3, 4 and 5 show the settings that enable the functions available in hardware mode. figure 7. hardware mode 2.5.1.1 pll clock reference (cis pin) the reference clock plays two roles: it centers the receive pll, and it provides the receive output clocks rsoclkp/rsockln and rpoclk in case of loss of signal. when the LXT6155 powers up, it looks for this reference clock to start-up internal blocks, including the receive pll circuitry. 2.5.1.1.1 ticlk this is the transmit input clock(s): either tsiclkp/tsiclkn in serial mode or tpiclk in parallel mode. 2.5.1.1.2 xtal xtal is an optional clock, created using an external crystal, connected across the xtalin and xtalout pins. the crystal provides an independent and stable clock source. this clock is also used as the reference for the tx clock monitoring circuitry. nevada hwsel rlis cis sp gnd remote loopback serial/parallel clock reference select local loopback llis mode line interface encode/ decode rife frame enable table 3. reference clock settings 1 cis clock reference note low ticlk default mode. the LXT6155 uses the transmit input clock as the reference clock for on chip operations. no crystal is needed. high xtal the LXT6155 uses the clock signal at xtalin as the reference clock for rx operation. this can either be an applied 19.44mhz clock or a 19.44mhz crystal can be connected across xtalin & xtalout. see table 24 for the crystal specifications. 1. for explanation, see clock sections below.
datasheet 21 155 mbps sdh/sonet/atm transceiver ? LXT6155 2.5.1.2 loopback test (rlis and llis pins) the LXT6155 allows two types of loopback test: remote loopback and local loopback. in remote loopback, the received data and clock are looped back to the transmit line interface. the LXT6155 still outputs recovered data and clock at the system interface. in local loopback, the transmit data is looped back to the receive input at the line interface. the LXT6155 also transmit data onto the line interface while looping back. for descriptive diagrams, please refer to figures 13 and 14. 2.5.1.3 line interface selection (mode pin) the mode pin sets one of the two line interfaces, as described in table 5. 2.5.1.4 parallel/serial mode selection (sp pin) in hardware mode, hwsel = low, the LXT6155 can be set to operate in serial or parallel data mode, depending on how the serial/parallel sp pin is set. setting the sp pin = high sets the LXT6155 to an 8-bit parallel mode. parallel pins tpid<7:0>, tpiclk, rpod<7:0>, rofp, rpoclk, lock and los are be used. serial pins tpos, tneg, tsiclkp, tsiclkn, rpos, rneg, rsoclkp, rsoclkn are unused and should be left open. setting the sp pin = low sets the LXT6155 to serial mode. pins tpos, tneg, tsiclkp, tsiclkn, rpos, rneg, rsoclkp, rsoclkn, lock and los are used. pins tpid<7:0>, tpiclk, rpod<7:0> and rpoclk are unused and should be left open. 2.5.1.5 tx amplitude trim in hardware, serial, coax mode, the line driver output amplitude can be controlled via pins 16 to 20. setting txtrimena (pin #20) high enables the trim capability. the trim rage is -21% to +24% in 3% steps controlled by txtrim0-txtrim3. the minimum amplitude is at 0000 and the maximum amplitude is at 1111. this is the same control range as in sw mode. table 4. loopback selection rlis llis description low low normal operation. no loopback testing. low high local loopback test activate. high low remote loopback test activate. high high table 5. mode line interface settings mode description low sets lvpecl nrz mode to interface to a fiber optic module. cmi related blocks (e.g. input/output buffers, equalizer) are disabled. high sets cmi mode to interface to a transformer and a 75 ? coax cable. nrz related input/output buffers are disabled.
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 22 datasheet 2.5.2 software mode when hwsel = high, the LXT6155 operates in software mode. control is through an external serial p interface. figure 8 shows the pins used in software mode. the LXT6155 uses four pins for the industry standard serial control interface (scp) bus: sclk, cs , sdi and sdo. sclk is the serial input control clock pin. cs is the chip select input. sdi is the serial data input pin, and sdo is the serial data output pin. figures 9 and 10 show the serial interface data structure. a data transaction is initiated by a falling edge on the chip select pin cs . a high-to-low transition on cs is required for each access to the control registers. the first bit is a read/write bit (r/w ), followed by seven address bits (a<6:0>), and eight data bits (d<7:0>). every data transaction requires 16 sclk cycles to complete. if r/w = high (read), the LXT6155 outputs a data byte d<7:0> on the sdo pin. if r/w = low (write), the LXT6155 accepts a data byte d<7:0> on the sdi pin, while tristating sdo pin. it is recommended in sw mode operation, the registers are first initialized by writing a ?0? to register #11 bit #6 (reset ). 2.5.2.1 serial input clock (sclk) this pin accepts a clock up to 4.096 mhz for data transactions between the LXT6155 and the scp bus. the LXT6155 clocks sdo data out on the falling edge, and clocks sdi data in on the rising edge of sclk (see figures 9 and 10). 2.5.2.2 chip select input (cs ) on the falling edge of cs , the LXT6155 starts data transactions. on the rising edge of cs ,the LXT6155 stops data transaction. the cs pin must be held low for at least 16 sclk cycles to complete a full read or write data transaction. if cs is held low less than 16 sclk cycles, then the data transaction is ignored. at the end of each write/read transaction, cs must return high, between the 16th and 17th clock edges. 2.5.2.3 serial input word (sdi) figure 10 shows the serial interface input data word structure. when the first input bit r/w =low, a write operation is performed. the sclk clocks data in on the sdi pin during the second 8 bits d<7:0> of the write operation. data is clocked in on the rising edge of sclk. during the entire 16 bit operation, sdo remains tristated. refer to tables 6 through 22 for control register descriptions. 2.5.2.4 serial output word (sdo) the serial output word structure is shown in figure 9. when the first input bit r/w =high,aread operation is specified. sdo becomes active after a0 has been clocked in. the first bit out of sdo changes the state of sdo from high-z to a low/high. sdo is clocked out on the falling edge of sclk.
datasheet 23 155 mbps sdh/sonet/atm transceiver ? LXT6155 figure 8. software mode figure 9. serial data output word structure (read cycle: r/w =high) figure 10. serial data input word structure (write cycle: r/w =low) 2.6 serial system interface the serial interface permits the LXT6155 to communicate with an overhead termination device at 155.52 mbps. data and clock lines are differential 3.3v lvpecl signals. refer to figure 11. 2.7 parallel system interface parallel interface allows the LXT6155 to communicate with the system chip at 19.44 mhz, 8 bits per clock cycle. data and clock lines are ttl compatible signals. refer to figure 12. LXT6155 hwsel cs sdi sclk vcc chip select in serial data in serial clock in sdo serial data out addr0, addr1 device address settings don't care a2 a1 a0 don't care sclk sdi cs sdo high impedance don't care a3 don't care a6 a5 a4 r/w =1 d7 d6 d5 d4 d3 d2 d1 d0 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 don't care sclk sdi cs sdo high impedance don't care a3 a6 a5 a4 r/w =0
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 24 datasheet figure 11. serial interface figure 12. parallel interface 2.8 loopback modes the LXT6155 provides two loopback modes that can be executed in either hardware or software mode: local loopback and remote loopback. in remote loopback mode, the crystal reference clock is used to center the receive pll to prevent illegal clock looping. 2.8.1 local loopback local loopback routes the transmit line output signals (ttip and tring) back to the receive line inputs (rtip and rring). in this mode, the line transmit output signals are active (see figure 13). nevada overhead terminator/atm uni data_out<0:1> clk_out<0:1> tpos, tneg tsiclkp, tsiclkn 4 data_in<0:1> 4 rpos, rneg clk_in<0:1> rsoclkp, rsoclkn los cmierr, los 4 cs sdi sdo sclk processor (optional) data i/o chip select clock 9 nevada overhead terminator/atm uni chip select data i/o clock cs sdi sdo sclk processor (optional) data_in<0:7> byte_rclk rpod<0:7> rpoclk data_out<0:7> byte_tclk tpid<0:7> tpiclk 9 los, rifp los, rofp/ cmierr 2 4
datasheet 25 155 mbps sdh/sonet/atm transceiver ? LXT6155 2.8.2 remote loopback remote loopback routes the receive system output signals, both data and clock, to the transmit system input (see figure 14). in this mode, system outputs (rpod<7:0> or rpos/rneg) are still active. figure 13. local loopback figure 14. remote loopback line buffer equalizer p/s pll s/p ttip0, tring0, ttip1, ttip1 rtip, rring tpid <7:0>, tpiclk, tpos/tneg, tsiclkp/n rpod <7:0>, rpoclk, rpos/rneg, rsoclkp/n line buffer equalizer p/s s/p pll tpid <7:0>, tpiclk, tpos/tneg, tsiclkp/n rpod <7:0>, rpoclk, rpos/rneg, rsoclkp/n ttip0, tring0, ttip1, ttip1 rtip, rring
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 26 datasheet 3.0 register definitions there are a total of sixteen (16) control registers in the LXT6155 addressed by the lowest four address bits, a<3:0>. see tables 8 through 22 for details . table 6. device address/control byte a<6:0> description a<6:5> LXT6155 device select. by using pins addr1 and addr0, up to four LXT6155 devices can be addressed. for a successful data transaction to occur, a6 and a5 must match the polarity settings on addr1 and addr0, respectively. using these controls, up to four LXT6155 devices can be independently controlled. a4 not used. set to 0 during transactions. a<3:0> LXT6155 register map (see table 7). table 7. LXT6155 register map (a<3:0>) register # a<3:0> register name type 0 0000 primary control r/w 1 0001 transmit control r/w 2 0010 transmit pll1 r/w 3 0011 transmit pll2 r/w 4 0100 equalizer load r/w 5 0101 equalizer/agc r/w 6 0110 matching filter2 r/w 7 0111 slicer r/w 8 1000 receive pll 1 r/w 9 1001 receive pll 2 r/w 10 1010 test r/w 11 1011 reset and bias r/w 12 1100 receive digital 1 r/w 13 1101 receive digital 2 r/w 14 1110 status/interrupt control r/w 15 1111 status/inter rupt output read-only
datasheet 27 155 mbps sdh/sonet/atm transceiver ? LXT6155 . table 8. primary control register settings, register #0 (address a<3:0>=0000) bit default mnemonic description 7 0 lpbk_cntl local loopback: 0 = no loopback 1 = activate local loopback 6 0 remote loopback: 0 = no loopback 1 = activate remote loopback 5 0 pll_ref pll/equalizer reference clock control: 0=usetpiclkclock 1 = use external crystal (xtalin) 4 0 - not used 3 1 clk_inv t piclk polarity at system interface: 0=tpid<7:0>sampledontherisingedgeoftpiclk 1 = tpid <7:0> sampled on the falling edge of tpiclk 21 r poclk polarity at system interface: 0 = rpod <7:0> transitions on the rising edge of rpoclk 1 = rpod <7:0> transitions on the falling edge of rpoclk 1 0 sys_int systems interface mode selection: 0 = serial mode 1 = parallel 8 bit mode 0 0 media_sel media and line code selection: 0 = fiber (nrz) 1=coax(cmi) table 9. tx control, register #1 (address a<3:0>=0001) bit default mnemonic description 7 1 tx_ena tx output enable: 0 = outputs disabled 1 = outputs active 6 1 tx_dig_reset tx digital circuitry reset. this can be used to minimize power comsumption when the device is disabled but not powered down. it must be enabled when the device is active. 0=reset 1=active 50 4:1 0.1.1.1 tx_amp_trim transmit amplitude trim: 0000 = -21% 1111 = +24% 0 1 tx_clk_sw_ena tx clock detection enable. this must be disabled in sw mode when pll_ref=0 (reg#0<5>=0) 0=disable 1 = enable
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 28 datasheet . . table 10. transmit pll1, register #2 (address a<3:0>=0010) bit default mnemonic description 7:5 0.1.1 not for customer use 4:3 0.0 not for customer use 2:1 1.0 not for customer use 0 1 not for customer use table 11. transmit pll2, register #3 (address a<3:0>=0011) bit default mnemonic description 7 1 not for customer use 6 1 not for customer use 5 1 not for customer use 4 0 not for customer use 3 0 not for customer use 2 0 not for customer use 1:0 1.0 not for customer use table 12. equalizer load, register #4 (address a<3:0>=0100) bit default mnemonic description 7 0 not for customer use 6:2 0.0.0.0.0 not for customer use 1 0 not for customer use 0 1 not for customer use table 13. equalizer & agc, register #5 (address a<3:0>=0101) bit default mnemonic description 7 1 eq_adapt_enab equalizer adaption enable: 0 = freeze adaption 1 = activate adaption 6:5 0.0 eq_adapt_gain equalizer adaption step size: 00 = 1 01 = 2 10 = 4 11 = 8 4 1 agc_adapt_ena agc adaption enable: 0 = freeze adaption 1 = activate adaption
datasheet 29 155 mbps sdh/sonet/atm transceiver ? LXT6155 3:2 0.0 agc_adapt_gain agc adaption step size: 00 = 1 01 = 2 10 = 4 11 = 8 1 1 afe_ena analog front end enable (also enables matching filter oscillator core): 0 = disabled (no bias) 1 = enabled 00 table 13. equalizer & agc, register #5 (address a<3:0>=0101) (continued) bit default mnemonic description table 14. matching filter 2, register #6 (address a<3:0>=0110) bit default mnemonic description 7:5 0.1.0 not for customer use 4:3 1.0 not for customer use 2:1 0.0 not for customer use 0 1 not for customer use 1. this register is used in cmi (co-ax) mode only. table 15. slicer, register #7 (address a<3:0>=0111) bit default mnemonic description 7:4 0.0.0.0 not for customer use 31 - unused 2 0 not for customer use 1 0 not for customer use 0 0 not for customer use table 16. rxpll 1, register #8 (address a<3:0>=1000) bit default mnemonic description 7:5 0.1.1 not for customer use 4:3 0.0 not for customer use 2 0 not for customer use 1 0 unused 0 1 not for customer use
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 30 datasheet . table 17. rx pll 2, register #9 (address a<3:0>=1001) bit default mnemonic description 7 1 not for customer use 6 1 not for customer use 5:3 0.1.1 freq_det_pw frequency detector output pulse width ({1 to 8} * 6.43 ns) 2 1 not for customer use 1 1 not for customer use 0 1 not for customer use table 18. test, register #10 (address a<3:0>=1010) bit default mnemonic description 7 1 los_clk_ena enables rx clock switching under los/lock condition: 0 = disable 1 = enable 6 0 not for customer use 5:2 0.0.0.0 not for customer use 1 1 not for customer use 0 0 not for customer use table 19. register, bias and fuse controls, register #11 (address a<3:0>=1011) bit default mnemonic description 7 0 bias_pwrdn power down all bias generators. this bit can be used to power down all the active analog circuitry on the device. 0= active 1=power down 6 1 reg_reset register array reset , ignores remainder of transaction (active low). this register is write only. 5:2 1.0.0.0 not for customer use 1:0 0.0 not for customer use table 20. rx digital 1, register #12 (address a<3:0>=1100) bit default mnemonic description 7 0 los_format combine (logical or) los/lock function onto los pin: 0 = disable 1 = enable 6 1 los_amp_trim amplitude los threshold trim: 0 = reduced alos dessert threshold (-3db) 1 = nominal alos thresholds
datasheet 31 155 mbps sdh/sonet/atm transceiver ? LXT6155 . . 5:4 1.1 los_ena los disable controls (amplitude los & digital los): 0=disable 1 = enable 3 0 frame_ena byte align enable: if used, this feature must be enabled during system configuration prior to applying data to the receiver. if this is not possible see application note an141 for further details. 0 = byte align disabled 1 = byte align enabled 2 0 not for customer use 1 0 not for customer use 0 1 not for customer use table 20. rx digital 1, register #12 (address a<3:0>=1100) (continued) bit default mnemonic description figure 15. rx digital 2, register #13 (address a<3:0>=11001) bit default mnemonic description 7 1 rx_dig_reset rx digital circuitry reset. this can be used to minimize power comsumption when the device is disabled but not powered down. it must be enabled when the device is active 0=reset 1 = normal operation 6:3 0.0.0.0 cnffp frame pulse position. refer to figure 5 for usage. 2:1 1.0 los_tran_assert d-los transition density count for assertion: 00 = 128 01 = 512 10 = 3112 11 = 4096 a-los assertion integration period: 00 = 2048 bits 01 = 512 bits 10 = 128 bits 11 = 32 bits 0 1 los_tran_deassert d-los transition density count for de-assertion: 0 = 4/32 1 = sonet compliant 1 a-los de-assertion integration period: 0=0bits 1=128bits 1. sonet compliant los de-assertion refers to bellcore gr-253, pages 6-16 (section 6.2.1.1.1), recommendation r6-54, los alarm is de-asserted (cleared) when two valid frame headers have been received with no los events in the interval. table 21. status control, register #14 (address a<3:0>=1110) bit default mnemonic description 7:4 0.0.0.0 - unused 3:0 0.0.0.0 stat_cont status register (register #15) mux control (indirect addressing to increase read space)
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 32 datasheet table 22. read-only register #15 (address a<3:0>=1111) value of: stat_cont status output bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 (status register) analog los digital los tx clock activity alarm status sonet oof signal unused 3 rx pll frequency lock alarm unused 3 01 not for customer use not for customer use 02 not for customer use not for customer use 03 (fuse contents- upper bits) not for customer use 04 (fuse contents- upper bits) not for customer use not for customer use 05 1,2 (interrupt register) analog los interrupt (los_ana_i) digital los interrupt (los_dig_i) tx clock alarm interrupt oof interrupt (oof_i) unused 3 unused 3 rx pll frequency lock alarm interrupt (rx_lock_i) cmi coding error alarm interrupts (cmi_err_i) 06 4 (device id) msb lsb 1. bits 7:1 are cleared upon reading the status register (stat_cont = 00). 2. bit 0 is cleared upon reading interrupt register (stat_cont = 05). 3. ignore these bits during register transactions, unpredictable contents 4. contains device revision number in hexadecimal notation.
datasheet 33 155 mbps sdh/sonet/atm transceiver ? LXT6155 4.0 application information the following provides application examples of interfacing the LXT6155 to the line side and the overhead terminator side. line side encoding schemes can be one of two types: lvpecl nrz encoded for a fiber optic module, or cmi encoded for a 75 ? coax cable. on the systems side, serial differential or parallel eight-bit modes can be used. all signals are ttl level compatible, except serial interface signals (tpos, tneg, tsiclkp, tsiclkn, rsoclkp, rsoclkn, rpos, and rneg) which are 3.3v lvpecl compatible. 4.1 fiber optic module interface the LXT6155 is designed to directly drive a 3.3v lvpecl fiber optic transceiver. the lvpecl drivers require the proper transmission line impedance to correctly drive the fiber module. signal traces should be 50 ? controlled impedance lines and should be biased to the appropriate level. please refer to figure 16 for the proper interface. to interface the LXT6155 lvpecl signals to a 5v pecl fiber optic module, please refer to the LXT6155 application note an141. 4.2 coax interface as shown in 17 on page 35, the LXT6155 directly drives a transformer connected to a 75 ? coaxial cable, up to12.7db cable loss at 78mhz. this is approximately 110m of rg59u. please refer to manufacturers specifications for maximum cable lengths. output cmi waveform conform to the itu g.703 specifications. rise and fall times are less than 2.0 ns. .
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 34 datasheet figure 16. 3.3 v lvpecl to 3.3 v lvpecl interface 50 ohm controlled impedance rd rd* td td* 3.3v fiber optic module r1 r2 r3 r4 vcc r7 r8 r5 r6 vcc LXT6155 ravcc well rdvcc pvcc vcc tdvcc tavcc ragnd sub rdgnd gnd tdgnd ragnd vbias rtip rring ttip1 tring1 txish atst rxish tavcc dvcc ravcc 15k, 1% 68nf nc 330 nf LXT6155 41 42 35 53 11 50 57 5 25 38 6 46 58 52 51 63 62 47 4 48 49 1) r1,r2,r5,r6 = 127 ohms, 1% 2) r3,r4,r7,r8 = 87.5 ohms 1% 3) transmission lines should be 50 ohm, controlled impedance strip lines. keep length as short as possible. 4) vcc = 3.3v for both resistor network, and fiber optic module.
datasheet 35 155 mbps sdh/sonet/atm transceiver ? LXT6155 figure 17. 75 ? coax cable interface 75 ohm coax 37.5 ohm strip line 75 ohm, 1% LXT6155 ravcc well rdvcc pvcc vcc tdvcc tavcc ragnd sub rdgnd gnd tdgnd ragnd vbias rtip rring ttip0 tring0 txish atst rxish tavcc dvcc ravcc 15k, 1% 68nf nc 330 nf LXT6155 41 42 35 53 11 50 57 5 25 38 6 46 58 52 51 61 60 47 4 48 49 1:1 75 ohm coax 1:1 37.5 ohm, 1% vcc 37.5 ohm, 1% 1.0 uf 1.0 nf 37.5 ohm strip line 75 ohm strip line 1.0 nf 1.0 uf table 23. transformer specifications parameter min typ max unit notes transmission, s12 -3db low 10 mhz -3db high 320 - mhz return loss, s11 -20db low 5 mhz -20db high 250 - mhz in-band loss 0.5 db 30 mhz ~ 300 mhz common mode rejection -10 db dc~250mhz cross-talk in dual packages -40 db dc~156mhz turns ratio 0.97 1.0 1.03
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 36 datasheet table 24. crystal specifications parameter min typ max unit notes center frequency 19.44 mhz freq tolerance -20 20 ppm at 25 c temperature drift -20 20 ppm -40 ~ 85 c aging -10 10 ppm first 10 years mode fundamental shunt capacitance 5 pf equivalent resistance 8.4 w temperature range -40 85 c
datasheet 37 155 mbps sdh/sonet/atm transceiver ? LXT6155 5.0 test specifications information in table 25 through 34 and figures 18 through 28 represent the performance specifications of the LXT6155 and are guaranteed by test, except as noted by design. table 25. absolute maximum ratings parameter sym min max unit dc supply (reference to gnd) vcc 4.0 v input voltage, ttl pins vin (ttl) gnd -0.3 5.5 v input voltage, other pins vin gnd -0.3 v cc +0.3 v input current, any pin iin -10 25 ma storage temperature tstg -65 150 c caution operating at or beyond these limits may result in damage to the device. normal operation not guaranteed at these extremes. table 26. recommended operating conditions parameter sym min typ max unit dc supply (referenced to gnd) vcc 3.0 3.3 3.6 v ambient operating temperature ta -40 25 85 c total current consumption serial/fiber serial/coax parallel/fiber parallel/coax 150 210 100 150 ma table 27. dc electrical characteristics (vcc=3.0vto3.6v;ta=-40 cto85c) parameter sym min typ 1 max unit test conditions high level input voltage (lvpecl) vih1 vcc-1.03 vcc-0.88 v low level input voltage (lvpecl) vil1 vcc-1.81 vcc-1.62 v high level output voltage (lvpecl) voh1 vcc-1.03 vcc-0.95 vcc-0.88 v 50 ? pulled down to v cc -2.0 v. low level output voltage (lvpecl) vol1 vcc-1.81 vcc-1.70 vcc-1.62 v high level input voltage (ttl) vih2 2.0 v low level input voltage (ttl) vil2 0.8 v high level output voltage (ttl) voh2 2.4 v i oh =4ma low level output voltage (ttl) vol2 0.4 v i ol =4ma input leakage current, low (ttl) ill 10 a input leakage current, high (ttl) ilh 10 a 1 typical values are at 25c and 3.3v. they are for design aid only; not guaranteed and not subject to production testing.
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 38 datasheet figure 18. transmit parallel input data timing (see table 28) figure 19. transmit serial input data timing (see table 28) table 28. transmit timing characteristics (see figures 18 and 19) parameter sym min typ 1 max unit test conditions transmit serial input clock frequency 155.52 mhz transmit serial input clock frequency error -20 +20 ppm compliant with gr253 transmit serial input clock duty cycle 45 55 % transmit serial input clock and data rise /fall time 2 1.2 ns 20% - 80% transmit parallel input clock frequency 19.44 mhz transmit parallel input clock frequency error -20 +20 ppm transmit parallel input clock duty cycle 45 55 % transmit parallel input data & clock rise/fall time 2 210ns tpiclk to tpid<0:7> hold time thtpid 3 ns tpiclk to tpid<0:7> setup time tstpid 2 ns tsiclkp(tsiclkn) to tpos (tneg) setup time tstpos 1.25 ns tsiclkp (tsiclkn) to tpos (tneg) hold time thtpos 0.75 ns 1. typical values are at 25c and 3.3v. they are for design aid only; not guaranteed and not subject to production testing. 2. not production tested, guaranteed by design and other correlation factors. thtpid tpiclk* tpid<0:7> tstpid *hw mode timing shown. in sw mode (hwsel=1) tpiclk polarity can be inverted. see table 8 for details. thtpos tsiclkp tpos tneg tstpos tsiclkn
datasheet 39 155 mbps sdh/sonet/atm transceiver ? LXT6155 table 29. transmit analog characteristics parameters note min typ 1 max unit test conditions transmit jitter generation 2 (intrinsic jitter sonet spec) 12 khz - 1.3 mhz 0.1 uipp prbs(23) pattern. transmit input data and clock have no input jitter. receive line input is all zeros. 0.01 uirms transmit jitter generation 2 (intrinsic jitter sdh spec) 500 hz - 1.3 mhz 1.5 uipp 65 khz - 1.3 mhz 0.075 uipp transmit jitter transfer function peaking 2 dc - 230 khz 0.4 db prbs(23) data. input jitter as showninfigure26. synthesizer capture range fcap -20 +20 ppm parallel mode synthesizer track range ftrack -20 +20 ppm synthesizer lock time tlock 100 s transmit output rise and fall times - cmi signals ttip0 tring0 2.2 ns 10% - 90% 0m cable length transmit output amplitude - cmi signals ttip0 tring0 0.9 1.1 vpp ttip0/tring0 output impedance zout 1.6 2.0 k ? 1. typical values are at 25c and 3.3v. they are for design aid only; not guaranteed and not subject to production testing. 2. not production tested, guaranteed by design and other correlation factors. table 30. receive timing characteristics (see figures 20 and 21) parameter sym min typ 1 max unit test conditions receive serial output clock frequency rsoclkp rsoclkn 155.52 mhz receive serial output clock duty cycle rsoclkdc 45 55 % receive serial output clock and data rise/fall time 2 -1.2ns 20% - 80%. rsoclkp/rsoclkn to rpos/ rneg propagation delay rsoclkpd -0.5 1.5 ns receive parallel output clock frequency rpoclk 19.44 mhz receive parallel output clock duty cycle rpocpdc 45 55 % receive parallel output data & clock rise/fall time rpoclkt 2 5 ns rpoclk to rpod<0:7> propagation delay rpoclkpd 0 7 ns rpoclk to rofp propagation delay rofppd 0 4 ns reference input clock into xtalin pin (ttl) refclk 19.44 mhz the refclk replaces the crystal 1. typical values are at 25c and 3.3v. they are for design aid only; not guaranteed and not subject to production testing. 2. not production tested, guaranteed by design and other correlation factors.
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 40 datasheet figure 20. receive serial output data timing (see table 30) figure 21. receive parallel output data timing (see table 30) reference clock offset from nominal -100 100 ppm table 30. receive timing characteristics (see figures 20 and 21) (continued) parameter sym min typ 1 max unit test conditions 1. typical values are at 25c and 3.3v. they are for design aid only; not guaranteed and not subject to production testing. 2. not production tested, guaranteed by design and other correlation factors. rsoclkn rsoclkp rpos rneg rsoclkpd rpoclk* rpod<0:7> rofp rpoclkpd rofppd *this shows timing in hw mode. in sw mode (hwsel=1) this clock polarity can be inverted. see table 8 for details. table 31. receive analog characteristics parameter note min typ 1 max unit test conditions end to end loss budget (coax) 1 - 15 db ber=1e-12. prbs (23) data. cmi encoded. input white noise =5mvrmsmax. los - fiber assert 20 sec nodatatransition.defaultlos setting. de-assert 187.5 sec no los events. default los settings. 1. typical values are at 25c and 3.3v. they are for design aid only; not guaranteed and not subject to production testing. 2. not production tested, guaranteed by design and other correlation factors.
datasheet 41 155 mbps sdh/sonet/atm transceiver ? LXT6155 los thresholds - coax assert 18 db attenuation measured at 78 mhz, cmi, 75 ? load. 12.7 db cable loss plus remaining flat loss. de-assert 17 db los hysteresis - coax hys 1.0 4.0 db measured from the level where los is asserted. prbs(23) data. receive jitter generation 2 (intrinsic jitter sonet spec) 12 khz - 1.3 mhz 0.01 uirms cmi encoded prbs(23) at rtip/rring with no data jitter. transmit input = all zeros refer to figure 27 and table 33. 0.1 uipp receive jitter generation 2 (intrinsic jitter sdh spec) 500 hz - 1.3 mhz 1.5 uipp 65 khz - 1.3 mhz 0.075 uipp receive jitter transfer peaking 2 dc - 230 khz 0.4 db prbs(23) data. input jitter as the max. tolerance curve showninfigure26. receive jitter tolerance 2 0.1 hz - 19.3 hz 39 uipp ber=1e-10. tolerated jitter meets figure 26 500hz-6.5khz 1.5 uipp 65 khz - 0.15 uipp pll nominal center frequency fnom 155.52 mhz pll capture range fcap -20 +20 ppm pll track range ftrack -20 +20 ppm pll lock time tlock 100 s prbs(23) pattern, from data applied at rtip/rring. device in fiber optic mode. equalizer adaptation time 500 bits from data applied line input impedance (rtip and rring) rin 4 k ? differential resistance parameter sym min typ max unit test conditions 1 rise/fall time - all ttl outputs trf 25 ns load 1.6ma, 50pf sdi to sclk setup time tdc 5 ns sclk to sdi hold time tcdh 5 ns sclk low time tcl 120 ns sclk high time tch 120 ns sclk rise and fall time tr, tf 25 ns cs to sclk setup time tcc 5 ns sclk to cs hold time tcch 5 ns cs inactive time tcwh 5 ns sclk to sdo valid tcdv 0 20 ns 1. typical values are at 25c and 3.3v. they are for design aid only; not guaranteed and not subject to production testing. table 31. receive analog characteristics (continued) parameter note min typ 1 max unit test conditions 1. typical values are at 25c and 3.3v. they are for design aid only; not guaranteed and not subject to production testing. 2. not production tested, guaranteed by design and other correlation factors.
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 42 datasheet figure 22. microprocessor input timing diagram figure 23. microprocessor output timing diagram sclk falling edge to sdo high z tcdz 0 20 ns cs rising edge to sdo high z tcz 0 20 ns parameter sym min typ max unit test conditions 1 1. typical values are at 25c and 3.3v. they are for design aid only; not guaranteed and not subject to production testing. cs t cwh t cch t cl t ch t cc sclk sdi t dc r/w t cdh control byte data byte sclk tcdz cs high z tcdv sdo tcz high z
datasheet 43 155 mbps sdh/sonet/atm transceiver ? LXT6155 figure 24. cmi encoded zero per g.703 and sts-3 figure 25. cmi encoded one per g.703 and sts-3 1ns v 1ns 1ns 1ns 1ns 1ns t1818930-92 positive transition at mid-unit interval negative transitions (note 1) (note 1) (note 1) nominal pulse nominal zero level (note 2) (note 1) 0.60 0.55 0.50 0.45 0.40 0.05 ?0.05 ?0.40 ?0.45 ?0.55 ?0.60 ?0.50 0.1 ns 0.1 ns 0.35 ns 0.35 ns 0.1 ns 1.608 ns 1.608 ns 0.1 ns t = 6.43 ns 1.608 ns 1.608 ns 1ns v 1ns 1ns t1818940-92 1ns positive transition negative transition (note 1) (note 1) (note 1) nominal pulse nominal zero level (note 2) 0.60 0.55 0.50 0.45 0.40 0.05 ?0.05 ?0.40 ?0.45 ?0.55 ?0.60 ?0.50 0.1 ns 0.1 ns 3.215 ns 3.215 ns 1.2 ns 1.2 ns 1.608 ns 1.608 ns 0.5 ns 0.5 ns t = 6.43 ns
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 44 datasheet note: the maximum ?steady state? amplitude should not exceed the 0.55 v limit. overshoots and other transients are permitted to fall into the dotted area. note: with the signal applied, the vertical position of the trace can be adjusted with the objective of meeting the limits of the masks. any such adjustment should be the same for both masks and should not exceed 0.05 v. figure 26. jitter tolerance table 32. jitter tolerance (in uipp) frequency oc3 stm1 10 hz 15 19.3 hz 39 30 hz 15 300 hz 1.5 500 hz 1.5 6.5 khz 1.5 1.5 65 khz 0.15 0.15 1.3 mhz 0.15 0.15 0.1 1 10 100 1hz 10hz 100hz 1khz 10khz 100khz 1mhz 10mhz frequency input jitter [ui(pk-pk)] measured data oc3 template stm1 template
datasheet 45 155 mbps sdh/sonet/atm transceiver ? LXT6155 figure 27. generation measurement filter characteristics table 33. jitter generation signal f1 f2 measured jitter oc3 12 khz 1.3 mhz 0.01 ui rms 0.1 uipp stm1 500 hz 1.3 mhz 1.5 uipp 65 khz 1.3 mhz 0.075 uipp table 34. jitter transfer signal f1 a1 unit oc3 230 khz 0.4 db stm1 230 khz 0.4 db f1 f2 0db
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 46 datasheet figure 28. typical coax jitter transfer note: measured with the device in remote loopback. data reflects total jitter in both tx and rx path -40 -30 -20 -10 0 10 1 10 100 1000 10000 100000 1000000 1000000 0 frequency [hz] gain coax mode LXT6155 spec. itu g.825 template a 1 f 1
datasheet 47 155 mbps sdh/sonet/atm transceiver ? LXT6155 figure 29. typical fiber jitter transfer note: measured with the device in remote loopback. data reflects total jitter in both tx and rx path -40 -30 -20 -10 0 10 1 10 100 1000 10000 100000 1000000 1e+07 frequency [hz] gain fiber mode LXT6155 spec. itu g.825 spec. f 1 a 1
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 48 datasheet 6.0 mechanical specifications figure 30. LXT6155le package specification d d 1 e e 1 for sides with even number of pins e / 2 for sides with odd number of pins e a 1 a 2 l a b l 1 3 3 64-pin low-profile quad flat pack ? part number LXT6155le ? extended temperature range: -40 to 85 c dim inches millimeters min max min max a.063 1.60 a1 .002 .006 0.05 0.15 a2 .053 .057 1.35 1.45 b .007 .011 0.17 0.27 d0.472 bsc 1 12.00 bsc 1 d1 0.394 bsc 1 10.00 bsc 1 e0.472 bsc 1 12.00 bsc 1 e1 0.394 bsc 1 10.00 bsc 1 e0.020 bsc 1 0.50 bsc 1 l 0.018 0.030 0.45 0.75 l1 0.039 ref 1.00 ref 311 13 11 13 q0 7 0 7 1. bsc ? basic spacing between centers
datasheet 49 155 mbps sdh/sonet/atm transceiver ? LXT6155 7.0 notes
LXT6155 ? 155 mbps sdh/sonet/atm transceiver 50 datasheet

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